The fabrication of integrated chips can be broadly separated into two main sections, front-end-of-the-line (FEOL) fabrication and back-end-of-the-line (BEOL) fabrication. FEOL fabrication includes the formation of devices (e.g., transistors, capacitors, resistors, etc.) within a semiconductor substrate. BEOL fabrication includes the formation of one or more metal interconnect layers comprised within one or more insulating dielectric layers disposed above the semiconductor substrate. The metal interconnect layers of the BEOL electrically connect individual devices of the FEOL to external pins of an integrated chip.
As the size of a semiconductor device size decreases, there is a trend towards thinner films being used for the diffusion barrier layer. Physical vapor deposition (PVD) process used for depositing a thinner barrier layer encounters difficulties in advanced scale of interconnection. Accordingly, a need has developed in the art for an improved method of forming an interconnect structure for an integrated chip.